1. Field of the Invention
The present invention relates to a timing generating circuit included in a RAM macro, and a RAM macro including the timing generating circuit.
2. Description of the Related Art
Conventionally, there are testing circuits for testing a RAM macro as disclosed, for example, by Patent Documents 1, 2, etc.
According to the invention disclosed by Patent Document 1, a fault of a memory cell is determined by causing access operations to be performed within a RAM at high speed with the use of an n-multiple (n is a real number) clock signal, which is generated by multiplying an externally input clock signal by n within a chip, as a clock signal for synchronizing operations within the RAM, and by making a comparison with an expected value only once at the end of one cycle of the externally input clock. Namely, whether or not the data itself of a RAM cell is changed by the influences of sequential accesses is evaluated with one pattern not by making a comparison with an expected value for each clock cycle, but by inputting a high-speed clock to either of X and Y sides and causing the sequential access operations to be performed.
Additionally, according to the invention disclosed by Patent Document 2, a command generating unit outputs a test clock generation signal if an instruction of a program for testing a memory is a test clock generation instruction. A timing test clock generating unit generates a test clock based on a timing margin clock with a phase different from a master clock, and the test cock generation signal. A timing test controlling circuit tests the memory by generating a signal for controlling the timing of the memory based on the master clock and the test clock.
Furthermore, not only a testing circuit where operation timings are determined based on an externally input clock CLK but also a testing circuit where operation timings are determined based on a clock other than a clock CLK is conventionally known as the above described testing circuit.
FIGS. 10A and 10B show examples of configurations of such conventional techniques.
A RAM macro 200 shown in FIG. 10A comprises a storing circuit 201, a controlling circuit 202, a timing generating circuit 203, and a testing circuit 204. The controlling circuit 202 performs various types of access operations to/from the storing circuit 201 based on externally input address, data, and various types of control signals, a signal (b) output from the timing generating circuit 203, and various types of control signals (c) output from the testing circuit 204 at the time of a test. The timings of various types of access operations are especially influenced by the operation timings of the various types of control signals (c) output from the testing circuit 204. In the configuration shown in FIG. 10A, the testing circuit 204 operates based on a control clock (a) output from the timing generating circuit 203. The control clock (a) is, for example, an n-multiple clock signal, etc. of a clock CLK.
A RAM macro 300 shown in FIG. 10B has only a difference from the configuration shown in FIG. 10A such that a test clock (d) that is a clock other than the clock CLK is externally input to the testing circuit 304, which operates based on the test clock (d).
With the conventional technique shown in FIG. 10A, the testing circuit generates the control timings of read and write operations from either of rising and falling timings of the externally input clock CLK, and cannot change only either of operation margins of the read and the write operations, leading to difficulties in identifying whether a fault is caused by either a read operation or a write operation.
Additionally, if the control timings of read and write operations are generated from the falling edge of the clock, a test must be conducted with high-frequency cycles in order to beforehand evaluate the margins of operations performed on high-frequency cycles equivalent to those on which the system is running. This requires a dedicated testing circuit to be separately embedded.
Furthermore, with the conventional technique shown in FIG. 10B, control signals (e) and (f) shown in this figure can be generated respectively from the timings of two types of clock signals by externally inputting the two types of clock signals (clock CLK and the test clock (d)). However, a circuit dedicated to the generation of the test clock (d) must be separately provided, and it becomes difficult to adjust the mutual timings of the two types of externally input clock signals. Therefore, it is desirable to enable fundamental timings of two systems or more with different timings to be generated based on a reference clock signal CLK within a RAM macro without using externally and separately generated clock signals.
Still further, the operation timings of various types of control signals output from the testing circuit cannot be conventionally changed to diverse timings with ease depending on a situation.    Patent Document 1: Japanese Published Unexamined Patent Application No. 2004-22014    Patent Document 2: Japanese Published Unexamined Patent Application No. 2004-158144